Design a 4-bit serial binary adder using three 4-bit shift registers, one full adder, and a D flip-flop. Two unsigned numbers are stored in two of the shift registers, A and B. Bits are added one pair at a time sequentially starting with the least significant bits. The carry out of the full adder is transferred to the D flip-flop which output is used as an input carry for the next pair of bits. The sum bit from the S output of the full adder is transferred into the third shift register C.