1. A computer whose processes have 1024 pages in their address spaces keeps its page tables in memory. The overhead required for reading a word from the page table is 5 nsec. To reduce this overhead, the computer has a TLB, which holds 32 (virtual page, physical page frame) pairs, and can do a look up in 1 μsec. What hit rate is needed to reduce the mean overhead to 2 nsec?
2. The TLB on the VAX does not contain an R bit. Why?
3. How can the associative memory device needed for a TLB be implemented in hardware, and what are the implications of such a design for expandability?