Optimum Repeater Spacing: Chips in 2007 are expected to have transistors with a gate length of…

Optimum Repeater Spacing: Chips in 2007 are expected to have transistors with a gate length of 0.09 Lm and wires with a cross section of 0.18 x 0.18 /Lm. The capacitance per unit length of wire is expected to be unchanged. The reduction in gate length translates to a four-fold decrease in gate delay. Under these assumptions, what will the optimum repeater spacing be for these minimum-width wires in 2007? What propagation velocity does this correspond to? A large chip in 2007 is expected to be 30 mm on a side. How many “gate delays” will it take to traverse one side of a chip in 2007? How does this compare with the number of “gate delays” required to traverse one side of an 18-mm chip in 1997?

 

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